The present invention relates generally to integrated circuit designs, and more particularly to a static random access memory (SRAM) device with a low operation voltage.
Static random access memory (SRAM) is typically used for the temporary storage of data in a computer system. SRAM retains its memory state without the need of any data refresh operations as long as it is supplied with power. A SRAM device is comprised of an array of “cells,” each of which retains one “bit” of data. A typical SRAM cell may include two cross coupled inverters and two access transistors connecting the inverters to complementary bit-lines. The two access transistors are controlled by word-lines to select the cell for read or write operation. In read operation, the access transistors are switched on to allow the charges retained at storage nodes of the cross coupled inverters to be read via the bit line and its complement. In write operation, the access transistors are switched on and the voltage on the bit line or the complementary bit line is raised to a certain level to flip the memory state of the cell.
FIG. 1 schematically illustrates a typical six-transistor SRAM cell 100. The SRAM cell 100 is comprised of PMOS transistors 102 and 104, and NMOS transistors 106, 108, 110 and 112. The PMOS transistor 102 has its source connected to a supply voltage Vcc, and its drain connected to a drain of the NMOS transistor 106. The PMOS transistor 104 has its source connected to the supply voltage Vcc, and its drain connected to a drain of the NMOS transistor 108. The sources of the NMOS transistors 106 and 108 are connected together to a complementary supply voltage, such as ground voltage or Vss. The gates of the PMOS transistor 102 and the NMOS transistor 106 are connected together to a storage node 114, which is further connected to the drains of the PMOS transistor 104 and the NMOS transistor 108. The gates of the PMOS transistor 104 and the NMOS transistor 108 are connected together to a storage node 116, which is further connected to the drains of the PMOS transistor 102 and the NMOS transistor 106. The NMOS transistor 110 connects the storage node 116 to a bit line BL, and the NMOS transistor 112 connects the storage node 114 to a complementary bit line BLB. The gates of the NMOS transistors 110 and 112 are controlled by a word line WL. When the voltage on the word line WL is a logic “1,” the NMOS transistors 110 and 112 are turned on to allow a bit of data to be read from or written into the storage nodes 114 and 116 via the bit line BL and the complementary bit line BLB.
One drawback of the typical six-transistor SRAM cell 100 is that it requires a relatively high operation voltage Vdd, which becomes a bottleneck, for designing new generation SRAMs. As the semiconductor processing technology advances, integrated circuits become smaller in size, and their supply voltage Vcc becomes lower in order to reduce power consumption. However, because the operation voltage Vdd of the conventional SRAM cell 100 has to remain at a certain level, it becomes the bottleneck of the efforts in designing the new generation SRAM with lower supply voltage Vcc.
FIG. 2 illustrates a conventional two-port SRAM cell 200 comprised of PMOS transistors 202 and 204, and NMOS transistors 206, 208, 210, 212, 214, and 216. In write operation, the NMOS transistors 210 and 212 are turned on for allowing a logic “1” or “0” to be written into the storage nodes 218 and 220. In read operation, the NMOS transistor 216 is turned on and the read bit line BL is pre-charged to a high voltage. If the voltage at the storage node 218 is high, the NMOS transistor 214 will be turned on and the read bit line BL will be pulled low. If the voltage at the storage node 218 is low, the NMOS transistor 214 will be turned off, and the voltage on the read bit line BL will remain high.
It is understood by those skilled in the art of integrated circuit design that although the operation voltage applied to read word line WL can be set lower than that of the conventional six-transistor SRAM cell, the operation voltage applied to write word line WL cannot be lowered significantly. As such, what is needed is to design a new SRAM cell that can operate with low operation voltage in both read and write operation.